The fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. Typically, at least some of these devices are formed on active areas in the substrate. The active areas are electrically isolated from one another by isolation regions formed of, for example, shallow trench isolation (STI). The STI trench is typically filled with silicon oxide. The devices are interconnected, enabling the ICs to perform the desired functions. Interconnections include, for example, contact holes in an interlevel dielectric layer to provide contact to an active area of the substrate. The contact holes can be formed using damascene techniques.
In order to achieve higher packing density, borderless contacts have been introduced. In borderless contact schemes, the contact hole extends to the edge of the active area. In such case, alignment margin between the contact hole and the active area is greatly reduced, increasing the potential for, for example, contact to gate short. The problem is exacerbated by the continued shrinkage of feature sizes in ICs. Furthermore, as devices are scaled down to 65 nm technology node and beyond, the process window for contact etching shrinks considerably. For example, the amount of polymer deposition during etching must be carefully controlled to avoid, on the one hand, contact open due to excessive polymer deposition inside the contact hole and, on the other hand, oxide gauging in the STI area due to poor etch selectivity.
From the foregoing discussion, it is desirable to provide an improved method for forming borderless contacts in ICs.